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| Preliminary Technical Data FEATURES Wide bandwidth: 1 MHz to 4 GHz 80 dB dynamic range (3 dB) Stability over temperature: < 0.5 dB Low noise measurement/controller output (VOUT) Pulse response time: 10 ns Small footprint package: 3 mm x 3 mm LFCSP Supply operation: 2.7 to 5.5 V at 30 mA Fabricated using high speed SiGe process 1 MHz to 4 GHz, 80 dB Logarithmic Detector/Controller ADL5513 FUNCTIONAL BLOCK DIAGRAM NC CLPF NC 16 15 14 NC 13 DET DET DET DET DET I V 12 VO UT V P OS 1 IN HI 2 IN LO 3 I V 11 VS ET APPLICATIONS RF transmitter PA setpoint control and level monitoring Power monitoring in radiolink transmitters RSSI measurement in base stations, WLAN, WiMAX, radar V P OS 4 5 AD L5513 SLOPE CO NT RO L 6 10 COMM BA N D G AP RE FE RENC E 7 G AIN BIAS 8 9 TADJ NC NC NC NC Figure 1. GENERAL DESCRIPTION The ADL5513 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibel-scaled output. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in either measurement or controller modes. The ADL5513 maintains accurate log conformance for signals greater than 4 GHz. The input dynamic range is typically 80 dB (re: 50 ) with error less than 3 dB. The ADL5513 has 10 ns response time which enables RF burst detection to a pulse rate of beyond 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient temperature conditions. A supply of 2.7 V to 5.5 V is required to power the device. Current consumption is less than 30 mA, and decreases to TBD A when the device is disabled. The ADL5513 can be configured to provide a control voltage to a power amplifier or a measurement output from the VOUT pin. Because the output can be used for controller applications, special attention has been paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin. The feedback loop through an RF amplifier is closed via VOUT, the output of which regulates the amplifier's output to a magnitude corresponding to VSET. The ADL5513 provides 0 V to (VPOS - 0.1 V) output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage VOUT that increases linear-in-dB with RF input signal amplitude. The logarithmic slope is 20 mV/dB, determined by the VSET interface. The intercept is -95 dBm (re: 50 , CW input, 900 MHz) using the INHI input. These parameters are very stable against supply and temperature variations. Rev. PrA 6/08 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved. ADL5513 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Preliminary Technical Data ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 Typical Performance Characteristics ..............................................8 Evaluation Board Configuration Options ................................... 10 Outline Dimensions ....................................................................... 12 Ordering Guide............................................................................... 12 REVISION HISTORY Rev. PrA | Page 2 of 12 Preliminary Technical Data SPECIFICATIONS ADL5513 VS = 5 V, T = 25C, ZO = 50 , Pins INHI, INLO, ac-coupled , Single-ended drive, VOUT tied to VSET, Error referred to best-fit line (linear regression), unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Maximum Input Frequency 100 MHz Output Voltage: High Power in Output Voltage: Low Power in 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Conditions Min 0.001 PIN = -10 dBm, PIN = -60 dBm CW input, TA = +25C CW input, TA = +25C CW input, TA = +25 1.578 0.589 75 67 58 9 -66 0.421 0.467 0.496 0.63 0.696 0.0.556 21 -88.18 1500/TBD 1.59 0.59 78 71 68 8 -68 0.45 0.40 0.515 0.525 0.62 0.67 21 -89.07 1500/TBD Typ Max 4 Unit GHz V V dB dB dB Deviation from output at 25C -40C < TA < +85C; PIN = -10 dBm -40C < TA < +85C; PIN = -30 dBm -40C < TA < +85C; PIN = -50 dBm -40C < TA < +125C; PIN = -10 dBm -40C < TA < +125C; PIN = - 30 dBm -40C < TA < +125C; PIN = -50 dBm Logarithmic Slope Logarithmic Intercept Input Impedance 900 MHz Output Voltage: High Power in Output Voltage: Low Power in 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature dB dB dB dB dB dB mV/dB dBm /pF V V dB dB dB PIN = -10 dBm, PIN = -60 dBm CW input, TA = +25C CW input, TA = +25C CW input, TA = +25 Deviation from output at 25C -40C < TA < +85C; PIN = -10 dBm -40C < TA < +85C; PIN = -30 dBm -40C < TA < +85C; PIN = -50 dBm -40C < TA < +125C; PIN = -10 dBm -40C < TA < +125C; PIN = - 30 dBm -40C < TA < +125C; PIN = -50 dBm Logarithmic Slope Logarithmic Intercept Input Impedance dB dB dB dB dB dB mV/dB dBm /pF Rev. PrA | Page 3 of 12 ADL5513 Parameter 1900 MHz Output Voltage: High Power in Output Voltage: Low Power in 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Conditions PIN = -10 dBm PIN = -60 dBm CW input, TA = +25C CW input, TA = +25C CW input, TA = +25 Preliminary Technical Data Min Typ 1.61 0.6 78 71 68 7 -64 0.46 0.515 0.66 0.41 0.73 0.785 21 -89.87 1500/TBD 1.61 0.61 78 70 66 7 -63 0.43 0.497 0.598 0.635 0.727 0.676 21 -90.01 1500/TBD 1.62 0.61 80 74 72 7 -60 0.47 0.605 0.715 0.575 0.8 0.853 21 -90.56 1500/TBD Max Unit V V dB dB dB Deviation from output at 25C -40C < TA < +85C; PIN = -10 dBm -40C < TA < +85C; PIN = -30 dBm -40C < TA < +85C; PIN = -50 dBm -40C < TA < +125C; PIN = -10 dBm -40C < TA < +125C; PIN = - 30 dBm -40C < TA < +125C; PIN = -50 dBm Logarithmic Slope Logarithmic Intercept Input Impedance 2140 MHz Output Voltage: High Power in Output Voltage: Low Power in 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature dB dB dB dB dB dB mV/dB dBm /pF V V dB dB dB PIN = -10 dBm, PIN = -60 dBm CW input, TA = +25C CW input, TA = +25C CW input, TA = +25 Deviation from output at 25C -40C < TA < +85C; PIN = -10 dBm -40C < TA < +85C; PIN = -30 dBm -40C < TA < +85C; PIN = -50 dBm -40C < TA < +125C; PIN = -10 dBm -40C < TA < +125C; PIN = - 30 dBm -40C < TA < +125C; PIN = -50 dBm Logarithmic Slope Logarithmic Intercept Input Impedance 2600 MHz Output Voltage: High Power in Output Voltage: Low Power in 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature dB dB dB dB dB dB mV/dB dBm /pF V V dB dB dB PIN = -10 dBm, PIN = -60 dBm CW input, TA = +25C CW input, TA = +25C CW input, TA = +25 Deviation from output at 25C -40C < TA < +85C; PIN = -10 dBm -40C < TA < +85C; PIN = -30 dBm -40C < TA < +85C; PIN = -50 dBm -40C < TA < +125C; PIN = -10 dBm -40C < TA < +125C; PIN = - 30 dBm -40C < TA < +125C; PIN = -50 dBm Logarithmic Slope Logarithmic Intercept Input Impedance dB dB dB dB dB dB mV/dB dBm /pF Rev. PrA | Page 4 of 12 Preliminary Technical Data Parameter 3.6 GHz Output Voltage: High Power in Output Voltage: Low Power in 3.0 dB Dynamic Range 1.0 dB Dynamic Range 0.5 dB Dynamic Range Maximum Input Level, 1.0 dB Minimum Input Level, 1.0 dB Deviation vs. Temperature Conditions PIN = -10 dBm, PIN = -60 dBm CW input, TA = +25C CW input, TA = +25C CW input, TA = +25 Min Typ 1.6 0.6 78 71 66 5 -66 0.64 0.64 0.62 0.856 0.926 0.937 21 -90.57 TBD ADL5513 Max Unit V V dB dB dB Deviation from output at 25C -40C < TA < +85C; PIN = -10 dBm -40C < TA < +85C; PIN = -30 dBm -40C < TA < +85C; PIN = -50 dBm -40C < TA < +125C; PIN = -10 dBm -40C < TA < +125C; PIN = - 30 dBm -40C < TA < +125C; PIN = -50 dBm Logarithmic Slope Logarithmic Intercept Input Impedance dB dB dB dB dB dB mV/dB dBm /pF SETPOINT INPUT Voltage Range Current Limit Source/Sink OUTPUT INTERFACE Rise Time Fall Time POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Supply Current Pin VSET Log conformance error 1 dB Min Log conformance error 1 dB Max 1% change Input level = no signal to -10dBm, 10% to 90% CLPF = 10 pF Input level = no signal to -10dBm, 10% to 90% CLPF = 10 pF Pin VPOS 2.7 25C RF in =-55 dBm When disabled TBD TBD TBD 10 20 5 30 TBD VPOS - 0.7 V 5.5 V mA nS nS V mA A POWER-DOWN INTERFACE Logic Level Threshold Enable Time Disable Time Pin PWDN Logic LO enables Logic HI disables PWDN LO to OUT at 100% final value, CLPF = 10pF, RF in = -10 dBm PWDN HI to OUT at 10% final value, CLPF = 10pF, RF in = -10 dBm 143 100 V ns ns Rev. PrA | Page 5 of 12 ADL5513 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage: VPOS VSET Voltage Input Power (Single-Ended, Re: 50 ) Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 5.5V 0 V to VPOS TBD dBm TBD W TBDC/W TBDC -40C to +125C -65C to +150C 260C Preliminary Technical Data Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 6 of 12 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 NC 14 CLPF 16 NC 13 NC ADL5513 VPOS 1 INHI 2 INLO 3 VPOS 4 PIN 1 INDICATOR 12 VOUT 11 VSET 10 COMM 9 TADJ ADL5513 TOP VIEW (Not to Scale) 5 6 NC Figure 2. Table 3. Pin Function Descriptions Pin No. 1, 4 2 3 10 9 11 12 5, 6, 7, 8, 13, 15, 16 14 Mnemonic VPOS INHI INLO COMM TADJ VSET VOUT NC CLPF Description Positive supply Voltage (VPOS), 2.7 V to 5.5 V RF input. AC -coupled RF input. RF common for INHI. AC- coupled RF common. Device Common. Temperature Compensation Adjustment. Frequency Dependant Temperature Compensation is set by connecting a ground referenced resistor to this pin. Setpoint Input for Operation in Controller Mode. To operate in RSSI mode short VSET to VOUT. Logarithmic/ Error Output. No Connect. These pins may be left open or soldered to a low impedance ground plane. Loop Filter Capacitor. In measurement mode, this capacitor sets the pulse response time and video bandwidth. In controller mode, the capacitance on this node sets the response time of the error amplifier/integrator. Internally connected to COMM; solder to a low impedance ground plane. Exposed Paddle Rev. PrA | Page 7 of 12 7 8 NC NC NC ADL5513 TYPICAL PERFORMANCE CHARACTERISTICS Preliminary Technical Data VPOS = 5 V; TA = +25C, -40C, +85C; +125C, unless otherwise noted. Black: +25C, Blue: -40C; Red: +85C, Orange: +125C. Error is calculated by using the best-fit line between PIN = -40 dBm and PIN = -10 dBm at the specified input frequency, unless otherwise noted. 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 Error (dB) VOUT (V) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 Error (dB) Error (dB) Error (dB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Figure 3 VOUT and Log Conformance vs. Input Amplitude at 100 MHz, Multiple Devices, VTADJ = 1.0 V 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 Error (dB) VOUT (V) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Figure 6 VOUT and Log Conformance vs. Input Amplitude at 100 MHz, VTADJ = 1.0 V 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Figure 4 VOUT and Log Conformance vs. Input Amplitude at 900 MHz, Multiple Devices, VTADJ = 0.975 V 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 Error (dB) VOUT (V) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Figure 7 VOUT and Log Conformance vs. Input Amplitude at 900 MHz, VTADJ = 0.975 V 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Figure 5 VOUT and Log Conformance vs. Input Amplitude at 1900 MHz, Multiple Devices, VTADJ = 0.925 V Figure 8. VOUT and Log Conformance vs. Input Amplitude at 1900 MHz, VTADJ = 0.925 V Rev. PrA | Page 8 of 12 Preliminary Technical Data 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 Error (dB) VOUT (V) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 ADL5513 3.0 2.5 2.0 1.5 1.0 Error (dB) Error (dB) Error (dB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0 5 10 Figure 9. VOUT and Log Conformance vs. Input Amplitude at 2140 MHz, Multiple Devices, VTADJ = 0.925 V 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 Error (dB) Figure 12. VOUT and Log Conformance vs. Input Amplitude at 2140 MHz, VTADJ = 0.925 V 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Figure 10. VOUT and Log Conformance vs. Input Amplitude at 2600 MHz, Multiple Devices, VTADJ = 0.9 V 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 Error (dB) Figure 13. VOUT and Log Conformance vs. Input Amplitude at 2600 MHz, VTADJ = 0.9 V 2.6 2.4 2.2 2 1.8 VOUT (V) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 Pin (dBm) -5 0 5 10 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 Figure 11. VOUT and Log Conformance vs. Input Amplitude at 3600 MHz, Multiple Devices, VTADJ = 0.9 V Figure 14. VOUT and Log Conformance vs. Input Amplitude at 3600 MHz, VTADJ = 0.9 V Rev. PrA | Page 9 of 12 ADL5513 EVALUATION BOARD CONFIGURATION OPTIONS Table 4. Evaluation Board Configuration Options Component C1, C2, R1 Preliminary Technical Data C3, C4, C5, C6, R11, R12 Function Input Interface. The 52.3 resistor in Position R1 combines with the internal input impedance of the ADL5513 to give a broadband input impedance of about 50 . C1 and C2 are dcblocking capacitors. A reactive impedance match can be implemented by replacing R1 with an inductor and C1 and C2 with appropriately valued capacitors. Power Supply Decoupling The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the ADL5513 and a 0.1 F capacitor placed nearer to the power supply input pin. If additional isolation from the power supply is required, a small resistance maybe installed in between the power supply and the ADL5513. (R11, R12) Filter Capacitor The low-pass corner frequency of the circuit that drives the VOUT pin can be lowered by placing a capacitor between CLPF and ground. Increasing this capacitor increases the overall rise/fall time of the ADL5513 for pulsed input signals. Output Interface--Measurement Mode. In measurement mode, a portion of the output voltage is fed back to the VSET pin via R4. The magnitude of the slope of the VOUT output voltage response can be increased by reducing the portion of VOUT that is fed back to VSET. R3 can be used as a backterminating resistor or as part of a single-pole, low-pass filter. Output Interface--Controller Mode. In this mode, R4 must be open. In controller mode, the ADL5513 can control the gain of an external component. A setpoint voltage is applied to Pin VSET, the value of which corresponds to the desired RF input signal level applied to the ADL5513 RF input. A sample of the RF output signal from this variable gain component is selected, typically via a directional coupler, and applied to ADL5513 RF input. The voltage at the VOUT pin is applied to the gain control of the variable gain element. A control voltage is applied to the VSET pin. The magnitude of the control voltage can optionally be attenuated via the voltage divider comprising R4 and R5, or a capacitor can be installed in Position R5 to form a low-pass filter along with R4. Temperature Compensation Interface. A voltage source can be used to optimize the temperature performance for various input frequencies. The pads for R8/R9 can be used for a voltage divider from the VPOS node to set the TADJ voltage at different frequencies. The ADL5513 may be disabled by by applying a voltage of VPOS -0.7 V to this node. Supply and Ground Connections Default Value R1 = 52.3 (Size 0402) C1 = 47 nF (Size 0402) C2 = 47 nF (Size 0402) C7 C3 = 0.1 F (Size 0402) C4 = 100 pF (Size 0402) C5 = 100 pF (Size 0402) C6 = 0.1 F (Size 0402) R11 = 0 (Size 0402) R12 = 0 (Size 0402) C7= 1000 pF (Size 0402) R2, R3 R4, R5, R10, RL, CL R4, R5, R10 R2 = open (Size 0402) R3 = 1 k (Size 0402) R4 = 0 (Size 0402) R5 = open (Size 0402) R10 = open (Size 0402) RL = CL = open (Size 0402) R4 = open (Size 0402) R5 = open (Size 0402) R10 = 0 (Size 0402) R6, R7, R8, R9 R6 = open (Size 0402) R7= 0 (Size 0402) R8 = open (Size 0402) R9 = open (Size 0402) VPOS, GND Not Applicable Rev. PrA | Page 10 of 12 Preliminary Technical Data VPOS GND ADL5513 VPOS C3 0.1 uF R11 0 ohms C7 1000 pF VOUT_ALT R2 open R3 1k R4 0 ohms TADJ C4 100 pF NC 15 NC 16 RFIN C1 47nF VPOS CLPF14 NC 13 VOUT CL open RL open VOUT 1 12 11 9 R5 open 2 INHI R1 52.3 ohms 3 INLO NC VPOS VSET ADL5513 COMM 10 6 NC C2 47nF 7 NC 8 NC 4 R10 0 ohms VSET 5 Z1 C5 100 pF R12 0 ohms R7 0 ohms VPOS C6 0.1 uF R6 open VPOS TADJ R8 open R9 open EXT_ PWDN - TADJ TADJ Figure 15. Evaluation Board Schematic Figure 16.Component Side Layout Figure 17. Component Side Silkscreen Rev. PrA | Page 11 of 12 ADL5513 OUTLINE DIMENSIONS a Preliminary Technical Data 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ ] 3 x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters 0.50 0.40 0.30 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 0.60 MAX PIN 1 INDICATOR 13 12 16 *1.65 1 1.50 SQ 1.35 EXPOSED PAD 9 (BOTTOM VIEW) 4 8 5 0.25 MIN 1.50 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 18. -Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADL5513-ACPZ-R7 1 ADL5513-ACPZ-R21 ADL5513-ACPZ-WP12 ADL5513-EVALZ1 1 2 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead LFCSP_VQ, Reel 16-Lead LFCSP_VQ, Reel 16-Lead LFCSP_VQ, Waffle Pack Evaluation Board Package Option CP-16-3 CP-16-3 CP-16-3 Branding TBD TBD TBD Z = RoHS Compliant Part. WP = waffle pack (c) 2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07514-0-6/08(PrA) Rev. PrA | Page 12 of 12 |
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